The Z3801A reports its current EFC value as either a percent (:DIAG:ROSC:EFC:REL?) or as an absolute value (:DIAG:ROSC:EFC:ABS?). A common question: what exactly is the correlation between one unit of EFC and frequency. For example if the reported EFC value changes by 5000 per week, what frequency drift does that imply?
There are several different approaches to determining this value. One of the easiest is to carefully watch a Z3801A coming out of an extended holdover. In this experiment my Z3801A#3 had been in holdover for several months and this provided a good opportunity to carefully watch a Z3801A come back to life from a long nap.
The EFC value and the output frequency were measured at one second intervals. The EFC value was obtained by issuing an EFC:ABS? command about once every second. The Z3801A output frequency was measured using a high-resolution frequency counter with a one second gate time. The log files were MJD time-stamped to allow correlation.
The GPS antenna was then reconnected. As the Z3801A came out of holdover, after it determined how far off in frequency the oscillator had drifted, it started adjusting the EFC to put the unit back to 10 MHz. As expected both the EFC changed and the output frequency changed.
The following is a plot of frequency during the first hour after reacquisition. The change in frequency is not instantaneous; the Z3801A goes easy on the end-user and it corrects the frequency error over the span of a few minutes. It over-shoots a bit and then for then next half hour it slowly comes closer to true 10 MHz.
For the purposes of watching jumps in both EFC and frequency we look only at the ramp of the first few minutes. Here is a plot showing in detail the initial moment that the frequency begins to be corrected. Notice the steps -- the frequency jumps. That's what we're looking for.
And similarly here is a plot of EFC during the same period, also showing steps (which is why the frequency jumped).
The above two plots already give us a hint that about 1000 units of EFC cause about a 5e-10 frequency change; so roughly 5e-13 change in frequency for a one unit change in EFC. Cool.
The offset and scale of the following two very long side-by-side plots has been adjusted so both curves match as closely as possible. The plots are very tall in order to show the EFC and frequency steps at high-resolution.
Thus one can conclude that one EFC unit represents a 5.20e-10 / 1000 = 5.2e-13 change in frequency.
This particular Z3801A changes in frequency by 5.2e-13 per EFC unit. It is likely that it varies slightly from unit to unit and from one end of the EFC curve to the other. But 5e-13/unit seems a good rule of thumb.
One can also observe from the frequency plot above that the short-term noise of the output of this Z3801A is about 1/2 of a plot division, or about 5e-12. On the EFC plot above one division is 20 EFC units. So one would not expect to be able to actually see the effect of a one unit EFC change on the output frequency -- it's in the noise. However, a jump of 10 or 20 units will begin to be visible (assuming the frequency counter has good enough resolution). A close look at the top of the side-by-side plots gives examples of small jumps in the range of 10 to 20 units.
Under stable conditions, with a low short-term noise Z3801A, a 16 unit EFC jump (equals one LSB of the 16-bit DAC) should be visible with a little but not too much frequency averaging.
There is a hint in the plots that frequency steps less than one DAC LSB (= 16 EFC units) are possible. In addition, after several tens of minutes the Z3801A descends into a mode where the EFC count never changes by more than plus or minus one unit at a time. If the 20-bit EFC count were simply truncated (dropping 4 bits) prior to feeding the 16-bit DAC no actual frequency change would occur until the EFC count changed by a net +16 or -16 units. This does not seem reasonable.
It is more likely that the DAC is operated in a PWM fashion where the 4-bit remainder controls the duty cycle of the LSB. This would also explain why there is a second order LPF on the output of the DAC.
A further clue is to monitor the latch pin of the AD569 DAC. In the trace below we see the DAC is, in fact, updated approximately 100 times a second.
|Z3801A U56 - AD569 - pin 23 - /LBE|
The AD569 DAC has 16 input pins, DB0 to DB15. Two nearby 74HC164 8-bit serial to parallel shift registers suggest the CPU manages the DAC serially:
As expected the clock pin of the shift register has the same 100 Hz rate.
|Z3801A U50 - HC164 - pin 8 - CP|
But wait, zooming in on the clock pin we see bursts of sixteen 1 µs clock pulses every 10 ms. So the Z3801A CPU clocks the 16 DAC bits in at 1 MHz into the shift register and latches the DAC at a ~100 Hz rate.
|Z3801A U50 - HC164 - pin 8 - CP|
Here is a trace showing the burst of serial clock pulses to load the shift register followed by the latch pulse to load the DAC:
|Shift register clock and DAC latch|
If we trigger off the first edge of the 16-pulse burst shift register clock input (pin 8) and trace the shift register input (pin 1) we can see the 16 bits being loaded into the DAC:
|Trace of 16-bit serial input to DAC|
The digital 'scope was set to 1 second persistence mode and, sure enough, we see that the low-order 3 bits are flickering: 1 and 0. There is an early bit prior to the first clock edge that looks like it isn't one of the DAC bits. The remaining 16 bits in this trace are clearly 1 0 1 1 1 0 0 0 0 0 0 0 0 x y z; where x, y, z appear to be randomly flickering 0 or 1.
If one issues a DIAG:ROSC:EFC:ABS? to this Z3801A the reply is +753722 (decimal) which in binary is 10111000000000111010. The first 13 high-order bits exactly match what we see on the 'scope!
Shifting by 4, expressing the EFC value as a 16-bit integer (for the DAC) plus 4-bit fraction (to dither), we get 1011100000000011.1010. In decimal this is 753722 / 16 = 47107.625 = 47107 10/16. Statically the DAC can generate 47107, or 47108, but to generate 47107.625 it must rapidly and cleverly alternate between two or more values such that the filtered average is 47107.625.
In this case it looks like it dithers the last three bits rather than just the last bit. In face, depending on the EFC value more or less bits are dithered. In any event, the average result will be a value between 47107 and 47108. A logic analyzer could be used to capture a long trace of the low-order 3 bits and the statistical average value computed.
But instead a 'scope in averaging mode will do. The trace then looks like:
|Trace of 16-bit serial input to DAC, averaged|
We can see the 'scope is doing the statistical average of each bit for us. The phantom bit (whatever it is) is on exactly half the time. The first 13 high order DAC bits are still clearly 1011100000000 (47104). Of the last 3 bits, the 3rd from the last bit appears about 40% of a logic 1, the 2nd from the last bit appears about 60% of a logic 1, and the last bit about 50% of a logic 1.
Adding these bit values up, we get 0.40 x 4 + 0.60 x 2 + 0.50 x 1 = 3.3. So on average the DAC is trying to generate the number in the neighborhood of 47104 + 3.3 = 47107.3. Not quite the precise value of 47107.625 that we were looking for, but at least these rough traces clearly show dithering of low-order bits of the 16-bit DAC in order to interpolate the full 20 bit EFC value. Very cool.
Below is a trace from another Z3801A showing 4 bits of dither. So the true picture is still a little more complicated than what has been described so far.
|A different Z3801A, a different EFC value|